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These figures describe the
•
Figure 6-13, "Data Test Command Register," on page 6-40
•
Figure 6-14, "Data Test Data 1 Register," on page 6-41
•
Figure 6-15, "Data Test Data 0 Register," on page 6-42
Access to these registers is possible only in Supervisor or Emulation mode.
When writing to
first, then the
DTEST_COMMAND
DTEST_COMMAND Register
When the Data Test Command register (
L1 cache data or tag arrays are accessed, and the data is transferred
through the Data Test Data registers (
The Data/Instruction Access bit allows direct access via the
DTEST_COMMAND
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
registers.
DTEST
registers, always write to the
DTEST
register.
MMR to L1 instruction SRAM.
DTEST_DATA
) is written to, the
DTEST_COMMAND
).
DTEST DATA[1:0]
Memory
registers
6-39
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