Analog Devices ADSP-BF53x Blackfin Reference page 40

Core Architecture
DA1 32
DA0 32
SD 32
LD1 32
LD0 32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
Figure 1-1. Processor Core Architecture
The compute register file contains eight 32-bit registers. When perform-
ing compute operations on 16-bit operand data, the register file operates
as 16 independent 16-bit registers. All operands for compute operations
come from the multiported register file and instruction constant fields.
1-2 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
ADDRESS ARITHMETIC UNIT
I3 L3 B3 M3
I2 L2 B2 M2
I1 L1 B1 M1
I0 L0 B0 M0
32
RAB
32
32
R7.L
R6.L
R5.L
16
R4.L
8
R3.L
R2.L
R1.H
BARREL
R0.L SHIFTER
A0
32
DATA ARITHMETIC UNIT
DAG1
DAG0
8 8
40
40 40
32
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
ASTAT
16
8
40
A1
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT