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6 MEMORY
Blackfin processors support a hierarchical memory model with different
performance and size parameters, depending on the memory location
within the hierarchy. Level 1 (L1) memories interconnect closely and effi-
cient with the Blackfin core for best performance. Separate blocks of L1
memory can be accessed simultaneously through multiple bus systems.
Instruction memory is separated from data memory, but unlike classical
Harvard architectures, all L1 memory blocks are accessed by one unified
addressing scheme. Portions of L1 memory can be configured to function
as cache memory. Some Blackfin derivatives also feature on-chip Level 2
(L2) memories. Based on a Von-Neumann architecture, L2 memories
have a unified purpose and can freely store instructions and data.
Although L2 memories still reside inside the
multiple
CCLK
external memory space that includes asynchronous memory space for
static RAM devices and synchronous memory space for dynamic RAM
such as SDRAM devices.
This chapter discusses the architecture and principles of on-chip memories
as well as memory protection and caching mechanisms. For memory size,
population, and off-chip memory interfaces, refer to the specific Blackfin
Processor Hardware Reference manual for your derivative.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
cycles to access. The processors also provide support of an
clock domain, they take
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6-1
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