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Performance Monitor Control Register (PFCTL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
0xFFE0 8000
PFCNT1
0 - Count number of cycles asserted
1 - Count positive edges only
PFCNT0
0 - Count number of cycles asserted
1 - Count positive edges only
15 14 13 12 11 10
X
PFCEN1[1:0]
00 - Disable Performance
Monitor 1
01 - Enable Performance
Monitor 1 in User
mode only
10 - Enable Performance
Monitor 1 in Super-
visor mode only
11 - Enable Performance
Monitor 1 in both User
and Supervisor modes
PEMUSW1
0 - Count down of performance
counter PFCNTR1 causes
exception event
1 - Count down of performance
counter PFCNTR1 causes
emulation event
PFMON0[7:0]
Refer to Event Monitor table on
page 21-22
Figure 21-13. Performance Monitor Control Register
Event Monitor Table
Table 21-8
identifies events that cause the Performance Monitor Counter
registers (
PFMON0
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
X
X
X
X
X
X
X
X
9
8
7
X
X
X
X
X
X
X
X
or
) to increment.
PFMON1
X
X
X
X
X
X
X
6
5
4
3
2
1
0
X
X
0
0
0
0
0
Debug
Reset = Undefined
PFMON1[7:0]
Refer to Event Monitor table on
page 21-22
PFPWR
0 - Performance Monitor
disabled
1 - Performance Monitor
enabled
PEMUSW0
0 - Count down of performance
counter PFCNTR0 causes
exception event
1 - Count down of performance
counter PFCNTR0 causes
emulation event
PFCEN0[1:0]
00 - Disable Performance
Monitor 0
01 - Enable Performance
Monitor 0 in User mode
only
10 - Enable Performance
Monitor 0 in Supervisor
mode only
11 - Enable Performance
Monitor 0 in both User and
Supervisor modes
21-21
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