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Memory Architecture
Blackfin processors support a modified Harvard architecture in combina-
tion with a hierarchical memory structure. Level 1 (L1) memories typically
operate at the full processor speed with little or no latency. At the L1 level,
the instruction memory holds instructions only. The two data memories
hold data, and a dedicated scratchpad data memory stores stack and local
variable information.
In addition, multiple L1 memory blocks are provided, which may be con-
figured as a mix of SRAM and cache. The Memory Management Unit
(MMU) provides memory protection for individual tasks that may be
operating on the core and may protect system registers from unintended
access.
The architecture provides three modes of operation: User, Supervisor, and
Emulation. User mode has restricted access to a subset of system resources,
thus providing a protected software environment. Supervisor and Emula-
tion modes have unrestricted access to the system and core resources.
The Blackfin processor instruction set is optimized so that 16-bit opcodes
represent the most frequently used instructions. Complex DSP instruc-
tions are encoded into 32-bit opcodes as multifunction instructions.
Blackfin products support a limited multi-issue capability, where a 32-bit
instruction can be issued in parallel with two 16-bit instructions. This
allows the programmer to use many of the core resources in a single
instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax. The
architecture is optimized for use with the C compiler.
Memory Architecture
The Blackfin processor architecture structures memory as a single, unified
4G byte address space using 32-bit addresses, regardless of the specific
Blackfin product. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of this
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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