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the memory-read operation to complete. If the instruction immediately
following the load uses the same register, it simply stalls until the value is
returned. Consequently, it operates as the programmer expects. However,
if four other instructions are placed after the load but before the instruc-
tion that uses the same register, all of them execute, and the overall
throughput of the processor is improved.
Ordering of Loads and Stores
The relaxation of synchronization between memory access instructions
and their surrounding instructions is referred to as weak ordering of loads
and stores. Weak ordering implies that the timing of the actual comple-
tion of the memory operations—even the order in which these events
occur—may not align with how they appear in the sequence of the pro-
gram source code. All that is guaranteed is:
• Load operations will complete before the returned data is used by a
subsequent instruction.
• Load operations using data previously written will use the updated
values.
• Store operations will eventually propagate to their ultimate
destination.
Because of weak ordering, the memory system is allowed to prioritize
reads over writes. In this case, a write that is queued anywhere in the pipe-
line, but not completed, may be deferred by a subsequent read operation,
and the read is allowed to be completed before the write. Reads are priori-
tized over writes because the read operation has a dependent operation
waiting on its completion, whereas the processor considers the write oper-
ation complete, and the write does not stall the pipeline if it takes more
cycles to propagate the value out to memory. This behavior could cause a
read that occurs in the program source code after a write in the program
flow to actually return its value before the write has been completed.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Memory
6-67
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