Instruction Overview
Compare Data Register
General Form
CC = operand_1 == operand_2
CC = operand_1 < operand_2
CC = operand_1 <= operand_2
CC = operand_1 < operand_2 (IU)
CC = operand_1 <= operand_2 (IU)
Syntax
CC = Dreg == Dreg ;
CC = Dreg == imm3 ;
CC = Dreg < Dreg ;
CC = Dreg < imm3 ;
CC = Dreg <= Dreg ;
(a) */
CC = Dreg <= imm3 ;
(a) */
CC = Dreg < Dreg (IU) ;
(a) */
CC = Dreg < uimm3 (IU) ;
*/
CC = Dreg <= Dreg (IU) ;
unsigned (a) */
CC = Dreg <= uimm3 (IU) ;
unsigned (a) */
Syntax Terminology
:
Dreg
R7–0
: 3-bit signed field, with a range of –4 through 3
imm3
: 3-bit unsigned field, with a range of 0 through 7
uimm3
11-2
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* equal, register, signed (a) */
/* equal, immediate, signed (a) */
/* less than, register, signed (a) */
/* less than, immediate, signed (a) */
/* less than or equal, register, signed
/* less than or equal, immediate, signed
/* less than, register, unsigned
/* less than, immediate, unsigned (a)
/* less than or equal, register,
/* less than or equal, immediate
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