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Hardware Errors and Exception Handling
Interrupt service routine can then read the cause of the error from the
5-bit
HWERRCAUSE
(
) and respond accordingly.
SEQSTAT
The Hardware Error Interrupt is generated by:
• Bus parity errors
• Internal error conditions within the core, such as Performance
Monitor overflow
• Peripheral errors
• Bus timeout errors
The list of supported hardware conditions, with their related
codes, appears in
appears in the
neously, only the last one can be recognized and serviced. The core does
not support prioritizing, pipelining, or queuing multiple error codes. The
Hardware Error Interrupt remains active as long as any of the error condi-
tions remain active.
4-60
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
field appearing in the Sequencer Status register
Table
4-10. The bit code for the most recent error
field. If multiple hardware errors occur simulta-
HWERRCAUSE
HWERRCAUSE
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