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Memory Protection and Properties
Memory Pages
The 4G byte address space of the processor can be divided into smaller
ranges of memory or I/O referred to as memory pages. Every address
within a page shares the attributes defined for that page. The architecture
supports four different page sizes:
• 1K byte
• 4K byte
• 1M byte
• 4M byte
Different page sizes provide a flexible mechanism for matching the map-
ping of attributes to different kinds of memory and I/O.
Memory Page Attributes
Each page is defined by a two-word descriptor, consisting of an address
descriptor word
xCPLB_DATA[n]
the page in memory. Pages must be aligned on page boundaries that are an
integer multiple of their size. For example, a 4M byte page must start on
an address divisible by 4M byte; whereas a 1K byte page can start on any
1K byte boundary. The second word in the descriptor specifies the other
properties or attributes of the page. These properties include:
• Page size
1K byte, 4K byte, 1M byte, 4M byte
• Cacheable/non-cacheable
Accesses to this page use the L1 cache or bypass the cache.
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
] and a properties descriptor word
xCPLB_ADDR[n
. The address descriptor word provides the base address of
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