Analog Devices ADSP-BF53x Blackfin Reference page 1020

Index
instruction pipeline
described, 4-3
stages, 4-7
stages (table), 4-7
instructions
See also specific instruction
16-bit parallel, 20-6
32-bit ALU/MAC, 20-3
ALU, 2-30, 2-32
byte align, 18-3
conditional, 2-24, 4-3
data cache control, 6-37
data cache lines, 17-1
FLUSH, C-101
in pipeline when interrupt occurs,
interlocked pipeline,
issuing in parallel, 20-1
JUMP, 7-2
linkage, 10-17
load / store, 6-66
multi-issue instruction,
multiplier, 2-38
program flow, 7-2
protected, 3-4
return, 3-5, 7-10
shifter, 2-53
store, 20-6
stored in memory, 6-65
synchronizing, 6-68
video pixel operations,
width, 4-8
instruction set, optimization of,
instruction summary, AAU,
instruction test command
(ITEST_COMMAND) register,
instruction test data (ITEST_DATAx)
registers, 6-22, 17-2
instruction test registers,
writing to, 6-20
I-18 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-67
6-66
20-1
18-1
1-4
5-20
6-21
6-19 to 6-23
instruction watchpoint address control
(WPIACTL) register,
instruction watchpoint address count
(WPIACNTn) registers, 21-5,
instruction watchpoint address (WPIAn)
registers, 21-5
instruction watchpoints, control bits,
integer
data format, D-1
mode, 2-15, D-6
multiplication, 2-45
integer multiplier results format,
internal memory
described, 1-5
L1 memory, 6-2
interrupt assignment register (IAR),
interrupt controller registers,
interrupt handling, instructions in pipeline,
4-67
interrupt mask (IMASK) register,
interrupt priority (IPRIO) register,
interrupts
cause, 1-7
control of system, 4-30
core, 6-34
definition, 4-30
disabling, 6-74, 16-13
enabling, 16-15
enabling and disabling,
force interrupt / reset (RAISE)
instruction, 16-17
for peripheral, 4-33
general-purpose, 4-30, 4-37,
generated by peripheral,
global enabling and disabling,
hardware error, 4-59
initialization, 4-34
IPRIO register, 6-35
multiple sources, 4-32
nested, 4-40, 4-51
21-7
21-6
21-4
2-17
1-8
B-6
16-15
6-35
6-74
4-47
4-31
4-48