Table of Contents
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Instruction Overview
• Assuming:
• register
•
R1
•
R0
then this instruction returns:
•
R6
•
R5
• Assuming:
• register
•
R1
•
R0
then this instruction returns:
•
R6
•
R5
• Assuming:
• register
•
R1
•
R0
then this instruction returns:
•
R6
•
R5
18-46
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
's two LSBs = 00b,
I0
= 0xFEED FACE
= 0xBEEF BADD
= 0x00FE 00ED
= 0x00FA 00CE
's two LSBs = 01b,
I0
= 0xFEED FACE
= 0xBEEF BADD
= 0x00DD 00FE
= 0x00ED 00FA
's two LSBs = 10b,
I0
= 0xFEED FACE
= 0xBEEF BADD
= 0x00BA 00DD
= 0x00FE 00ED
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