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The branch latency for conditional branches is as follows.
• If prediction was "not to take branch," and branch was actually not
taken: 0
• If prediction was "not to take branch," and branch was actually
taken: 8
• If prediction was "to take branch," and branch was actually taken:
4
cycles.
CCLK
• If prediction was "to take branch," and branch was actually not
taken: 8
For all unconditional branches, the branch target address computed in the
AC stage of the pipeline is sent to the Instruction Fetch Address bus at the
beginning of the DF1 stage. All unconditional branches have a latency of
4
cycles.
CCLK
Consider the example in
Table 4-4. Branch Prediction
Instruction
If CC JUMP dest (bp)
Hardware Loops
The sequencer supports a mechanism of zero-overhead looping. The
sequencer contains two loop units, each containing three registers. Each
loop unit has a Loop Top register (
), and a Loop Count register (
LB1
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
cycles.
CCLK
cycles.
CCLK
cycles.
CCLK
Table
4-4.
LC0
Program Sequencer
Description
This instruction tests the CC flag, and if it is set,
jumps to a location, identified by the label, dest.
If the CC flag is set, the branch is correctly pre-
dicted and the branch latency is reduced. Other-
wise, the branch is incorrectly predicted and the
branch latency increases.
,
), a Loop Bottom register (
LT0
LT1
,
).
LC1
,
LB0
4-21
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