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Addressing With the AAU
The DAGs can generate an address that is incremented by a value or by a
register. In post-modify addressing, the DAG outputs the I-register value
unchanged; then the DAG adds an M-register or immediate value to the
I-register.
In indexed addressing, the DAG adds a small offset to the value in the
P-register, but does not update the P-register with this new value, thus
providing an offset for that particular memory access.
The processor is byte addressed. All data accesses must be aligned to the
data size. In other words, a 32-bit fetch must be aligned to 32 bits, but an
8-bit store can be aligned to any byte. Depending on the type of data
used, increments and decrements to the address registers can be by 1, 2, or
4 to match the 8-, 16-, or 32-bit accesses.
For example, consider the following instruction:
R0 = [ P3++ ];
This instruction fetches a 32-bit word, pointed to by the value in
places it in
. It then post-increments
R0
with the 32-bit access.
R0.L = W [ I3++ ];
This instruction fetches a 16-bit word, pointed to by the value in
places it in the low half of the destination register,
post-increments
R0 = B [ P3++ ] (Z) ;
This instruction fetches an 8-bit word, pointed to by the value in
places it in the destination register,
maintaining alignment with the 8-bit access. The byte value may be zero
extended (as shown) or sign extended into the 32-bit data register.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
by two, maintaining alignment with the 16-bit access.
I3
Address Arithmetic Unit
by four, maintaining alignment
P3
R0.L
. It then post-increments
R0
, and
P3
, and
I3
. It then
, and
P3
by one,
P3
5-5
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