Analog Devices ADSP-BF53x Blackfin Reference page 1014

Index
evaluation of loop conditions,
event controller
activities managed, 4-29
MMRs, 4-38
processor mode, 3-1
sequencer, 4-3
tasks, 1-6, 4-3
event handling
activities managed, 4-29
nesting, 1-6
prioritization, 1-6
types supported, 1-7
event prioritization, 1-6
events
asynchronous, 1-6
definition, 4-29
emulation, 1-7, 3-1,
exception, 1-7, 4-61
incrementing PFMONx,
interrupt, 1-7
latency in servicing,
nested, 4-40
NMI, 1-7
processing, 4-3
reset, 1-7
synchronous, 1-6
triggering, 21-3
types of, 1-7
event vector table (EVT). See EVT
EVT (event vector table),
EVX (exception) bit, 4-40,
EX1 (execute 1), 4-7
EX1 stage, 4-9
EX2 (execute 2), 4-7
EX2 stage, 4-9, 4-20
EXCAUSE (exception cause) field,
exception core event, 4-30
exception events, 3-4
exception routine, example code,
I-12 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-22
4-45
21-21
4-56
4-31
4-41
4-59
4-70
exceptions
address violations not flagged,
17-9
alignment, 7-3, 8-8 to 8-50, 10-3, 10-7,
10-10, 10-15, 10-19
alignment errors prevented,
18-41
attempting to write protected memory,
6-53
by descending priority (table),
DAG0 CPLB miss, 4-66
DAG0 misaligned access,
DAG0 multiple CPLB hits,
DAG0 protection violation,
DAG1 CPLB miss, 4-66
DAG1 misaligned access,
DAG1 multiple CPLB hits,
DAG1 protection violation,
deferring, 4-68
defined, 1-7
emulation, 16-11
events, 4-63
events that cause, 4-61
force exception (EXCPT) instruction,
4-66, 16-20
graceful instruction abort, 10-6, 10-15,
10-18
handler, executing, 4-66
handler routine, 16-20
handling instructions in pipeline,
I-fetch access exception,
I-fetch CPLB miss, 4-65
I-fetch misaligned access,
I-fetch multiple CPLB hits,
I-fetch protection violation,
illegal combination,
illegal instruction, 16-11
illegal use protected resource,
MMRs, 6-73
MMU, 6-53
17-3 to
18-6 to
4-65
4-66
4-66
4-66
4-66
4-66
4-66
4-67
4-65
4-65
4-65
4-65
4-66
4-66