Analog Devices ADSP-BF53x Blackfin Reference page 826

Load / Store Instructions
Table C-10. Load / Store Instructions (Sheet 11 of 12)
Instruction
and Version
Store Low Data Register Half
W [ Ireg ] = Dreg_lo
Store Low Data Register Half
W [ Ireg ++ ] = Dreg_lo
Store Low Data Register Half
W [ Ireg – – ] = Dreg_lo
Store Low Data Register Half
W [ Preg ] = Dreg_lo
NOTE: Both Pointer Preg # fields must refer to the same Preg number. Otherwise, this opcode represents
a post-modify version of this instruction.
Store Low Data Register Half
W [ Preg ] = Dreg
Store Low Data Register Half
W [ Preg ++ ] = Dreg
Store Low Data Register Half
W [ Preg – – ] = Dreg
Store Low Data Register Half
W [ Preg + uimm5m2 ] = Dreg
Store Low Data Register Half
W [ Preg + uimm16m2 ] = Dreg
C-26 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x9F20— 1 0 0 1 1 1 1 1 0 0 1 Ireg # Dreg #
0x9F3F
0x9E20— 1 0 0 1 1 1 1 0 0 0 1 Ireg # Dreg #
0x9E3F
0x9EA0— 1 0 0 1 1 1 1 0 1 0 1 Ireg # Dreg #
0x9EBF
0x8A00— 1 0 0 0 1 0 1 Source
0x8BFF
0x9700— 1 0 0 1 0 1 1 1 0 0 Preg #
0x973F
0x9600— 1 0 0 1 0 1 1 0 0 0 Preg #
0x963F
0x9680— 1 0 0 1 0 1 1 0 1 0 Preg #
0x96BF
0xB400— 1 0 1 1 0 1 uimm5m2
0xB7FF
0xE640 0000— 1 1 1 0 0 1 1 0 0 1 Preg #
0xE67F 7FFF
uimm16m2 divided by 2
Bin
Pointer Pointer
Dreg # Preg # Preg #
Dreg #
Dreg #
Dreg #
Preg # Dreg #
divided by 2
Dreg #