Analog Devices ADSP-BF53x Blackfin Reference page 354

Instruction Overview
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Parallel Issue
This instruction can be issued in parallel with specific other instructions.
For more information, see "Issuing Parallel Instructions" on page 20-1.
Example
r3.l = w[ i1 ] ;
r7.l = w[ i3 ++ ] ;
r1.l = w[ i0 -- ] ;
r2.l = w[ p4 ] ;
r5.l = w[ p2 ++ p0 ] ;
Also See
Load High Data Register
Half-Word – Sign-Extended
Special Applications
To read consecutive, aligned 16-bit values for high-performance DSP
operations, use the Load Data Register instructions instead of these
Half-Word instructions. The Half-Word Load instructions use only half
of the available 32-bit data bus bandwidth, possibly imposing a bottleneck
constriction in the data flow rate.
8-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Half, Load Half-Word – Zero-Extended, Load