Analog Devices ADSP-BF53x Blackfin Reference page 679

Table 18-30. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
Flags Affected
None
The ADSP-BF535 processor has fewer
operate differently than subsequent Blackfin family products. For
more information on the ADSP-BF535 status flags, see
on page
Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
Example
saa (r1:0, r3:2) || r0 = [i0++] || r2 = [i1++] ; /* parallel fill
instructions */
saa (r1:0, r3:2) (R) || r1 = [i0++] || r3 = [i1++] ; /* reverse,
parallel fill instructions */
saa (r1:0, r3:2) ; /* last SAA in a loop, no more fill
required */
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
src_reg_pair_LO
byte7 byte6
byte6
A-3.
"Issuing Parallel Instructions" on page
Video Pixel Operations
src_reg_pair_HI
byte5 byte4 byte3
byte3
byte4 byte3
byte5 byte4 byte3
byte5 byte4 byte3
flags and some flags
ASTAT
byte2 byte1 byte0
byte2 byte1 byte0
byte2 byte1
byte2
Table A-1
20-1.
18-39