Analog Devices ADSP-BF53x Blackfin Reference page 1010

Index
copyback buffer, 6-35
core
architecture, 1-1 to 1-4,
double-fault condition,
double-fault reset, 3-13
waking up from idled state,
core architecture, contents of,
core event
emulation, 4-30
exception, 4-30
in EVT, 4-41
MMR location, 4-42
NIM, 4-30
reserved, 4-30
reset, 4-30
core event controller (CEC). See CEC
core event core timer, 4-30
core event vector table (table),
core interrupt latch (ILAT) register. See
ILAT
core interrupt mask (IMASK) register. See
IMASK
core interrupts pending (IPEND) register.
See IPEND
core MMRs, 6-73, B-1
core-only software reset, 3-13,
core synchronize (CSYNC) instruction,
16-5
core synchronize instruction,
core timer core event, 4-30
core timer interrupt (IVTMR) bit,
counter, cycle, 4-6, 21-23
counter register, loops,
count instructions, one's population count,
13-26
count value (WPDACNT[15:0]) field,
21-12
count value (WPIACNT[15:0]) field,
CPLB_DIRTY bit, 6-57
CPLB_L1_AOW bit, 6-57
I-8 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
2-2
4-46
4-34
1-1
4-42
3-16
C-99
4-47
7-17
21-7
CPLB_L1_CHBL bit, 6-55,
CPLB_LOCK bit, 6-55,
CPLB_LRUPRIO bit, 6-5, 6-16,
CPLBs
after reset, 6-26
defined, 6-46, 6-47
disabling, 6-6
enabling, 6-6, 6-10
enabling and disabling,
L1 instruction cache,
management, 6-50
replacement policy, 6-51
CPLB_SUPV_WR bit,
CPLB_USER_RD bit, 6-55,
CPLB_USER_WR bit,
CPLB_VALID bit, 6-55,
CPLB_WT bit, 6-57
C-style indexed stack manipulation,
CSYNC (core synchronize) instruction,
16-5
customer support, xxviii
cycle
counter, 21-23, 21-24
counter register, 4-6
cycle counter enable (CCEN) bit,
CYCLES ⁄ CYCLES2[15:0] field,
CYCLES ⁄ CYCLES2[31:16] field,
CYCLES2 (execution cycle count) register,
21-24
CYCLES (execution cycle count) register,
21-24
D
DAG0 CPLB miss, 4-66
DAG0 misaligned access,
DAG0 multiple CPLB hits,
DAG0 port preference (PORT_PREF0)
bit, 6-25, 6-26
DAG0 protection violation,
DAG1 CPLB miss, 4-66
6-57
6-57
6-55
6-26
6-10
6-57
6-57
6-57
6-57
1-3
21-26
21-25
21-25
4-66
4-66
4-66