Index
latency
in interrupt processing,
level 2 (L2) memory, 6-4,
servicing events,
4-56
when servicing interrupts,
LB (loop bottom) register, 1-14, 4-22,
LC (loop count) register, 1-14, 4-22,
leaf functions,
4-14
least recently used (LRU) algorithm
definition,
6-75
length (Lreg) registers, description,
length registers, initialization,
length registers (L[3:0]), 5-3, 5-8,
defined,
1-14
description,
1-22
function in circular addressing,
level 1 (L1) data memory,
architecture,
6-27
traffic,
6-24
level 1 (L1) instruction memory,
6-19
bank architecture,
6-8
configuration,
6-10
DAG reference exception,
enabled as cache,
6-53
instruction cache,
6-10
organization,
6-10
subbank organization,
level 1 (L1) memory,
1-4
See also level 1 (L1) data memory; level 1
(L1) instruction memory
about,
6-3
address alignment,
6-7
data cache,
6-29
definition,
6-75
frequency,
6-4
overview,
6-2
scratchpad data SRAM,
I-20
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-34
6-44
4-48
4-24
4-24
C-3
5-4
5-13
1-22
6-24
to
6-38
6-5
to
6-7
6-5
6-4
level 2 (L2) memory
CCLK cycles,
6-1
defined, 1-5,
6-43
enabling cache,
6-6
latency, 6-4,
6-44
latency with cache off,
latency with cache on,
non-cacheable,
6-45
overview,
6-4
line fill
buffers, 6-15,
6-34
cache,
6-14
linkage instruction, 10-17,
linkage instructions. See LINK, UNLINK
LINK instruction
code sequence,
4-17
subroutine example,
syntax,
10-17
little endian, definition,
little endian byte order,
load
operation,
6-66
ordering,
6-67
load byte – sign-extended instruction, 8-34,
C-22
load byte – zero-extended instruction, 8-31,
C-22
load data register instruction, 8-10,
load half-word – sign-extended instruction,
8-19,
C-20
load half-word – zero-extended instruction,
8-15,
C-19
load high data register half instruction,
8-23,
C-20
load immediate instruction, 8-3,
load instructions,
8-1
load byte – sign-extended, 8-34,
load byte – zero-extended, 8-31,
load half-word – sign-extended, 8-19,
C-20
6-45
6-44
C-38
4-18
6-75
2-13
C-17
C-16
C-22
C-22
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