Analog Devices ADSP-BF53x Blackfin Reference page 727

Valid pairs are
Dreg
Syntax
Separate the two compatible scalar instructions with a comma to produce
a vector instruction. Add a semicolon to the end of the combined instruc-
tion, as usual. The order of the MAC operations on the command line is
arbitrary.
Instruction Length
This instruction is 32 bits long.
Flags Affected
This instruction affects the following flags.
• is set if any result saturates; cleared if none saturates.
V
• is set if
VS
• All other flags are unaffected.
The ADSP-BF535 processor has fewer
operate differently than subsequent Blackfin family products. For
more information on the ADSP-BF535 status flags, see
on page
Example
r2.h=r7.l*r6.h, r2.l=r7.h*r6.h ;
/* simultaneous MAC0 and MAC1 execution, 16-bit results. Both
results are signed fractions. */
r4.l=r1.l*r0.l, r4.h=r1.h*r0.h ;
/* same as above. MAC order is arbitrary. */
r0.h=r3.h*r2.l (m), r0.l=r3.l*r2.l ;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, ,
R7:6 R5:4 R3:2
is set; unaffected otherwise.
V
A-3.
Vector Operations
, and .
R1:0
flags and some flags
ASTAT
Table A-1
19-39