Analog Devices ADSP-BF53x Blackfin Reference page 1009

code examples
loop, 4-22
prolog code for nested ISR,
recreating execution trace,
restoring control register,
using hardware loops in ISR,
code patching, 21-5
collision, address, 6-27
collision, cache address,
compare accumulator instruction, 11-9,
C-41
compare data register instruction, 11-2,
C-39
compare instructions
compare accumulator, 11-9,
compare data register, 11-2,
compare pointer, 11-6,
compare-select (VIT_MAX), 19-8,
C-107
compare pointer instruction, 11-6,
compare-select (VIT_MAX) instruction,
19-8, C-107
computational instructions,
computational status, using,
computational units, 2-1
computation stalls, 4-9
compute register file, 1-2
conditional
branches defined, 4-19
branch latency, 4-21
CSYNC instruction,
instructions, 2-24, 4-3
JUMP instruction, 4-10
register move, 4-20
speculative load execution example,
condition code (CC) bit. See CC bit
condition code (CC) flag bit,
constants
imm16, 8-4
imm3, 11-2, 11-6
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
4-53
21-18
6-74
4-28
6-29
C-41
C-39
C-40
C-40
2-1
2-24
to 2-56
6-69
6-69
4-18
constants
imm3 constant, 11-2
imm6, 14-21
imm7, 8-4, 15-16
lppcrel11m2, 7-14
notation convention, 1-11, 1-12, C-5,
C-6
pcrel11m2, 7-6
pcrel13m2, 7-2
pcrel25m2, 7-3, 7-8
pcrel5m2, 7-14
pcrelm2, 7-2
uimm15, 8-31, 8-34,
uimm16, 8-4
uimm16m2, 8-15, 8-19,
uimm17m4, 8-7, 8-11, 8-37,
uimm18m4, 10-17
uimm3, 11-2, 11-6
uimm4, 14-8, 14-15, 16-17, 16-20,
19-23, 19-28
uimm5, 13-2, 13-4, 13-6, 13-8, 14-8,
14-15
uimm5m2, 8-15, 8-19,
uimm6m4, 8-7, 8-11, 8-37,
uimm7m4, 8-7, 8-11, 8-37,
user_label, 7-3, 7-6,
constants, notation convention,
content-addressable memory (CAM),
control code bit management instructions,
C-39
control code (CC) bit
in ASTAT register, 11-1
moving status of, 11-13
controlling program flow,
control register
data memory, 6-24
instruction memory,
restoration, 6-74
conventions, xxxvi
convergent rounding, 1-19,
Index
(continued)
8-54
8-50
8-41
8-50
8-41
8-41
7-8
C-6
6-46
4-19
6-5
2-20
I-7