Analog Devices ADSP-BF53x Blackfin Reference page 869

Table C-17. Arithmetic Operations Instructions (Sheet 15 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate to Accumulator
Legend:
Dreg half determines which halves of the input oper-
and registers to use.
Dreg_lo * Dreg_lo
Dreg_lo * Dreg_hi
Dreg_hi * Dreg_lo
Dreg_hi * Dreg_hi
Dest. Dreg # encodes the destination Data Register.
src_reg_0 Dreg # encodes the input operand register to the left of the "*" operand.
src_reg_1 Dreg # encodes the input operand register to the right of the "*" operand.
Multiply and Multiply-Accumulate
to Accumulator
A0 = Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate
to Accumulator
A0 = Dreg_lo_hi * Dreg_lo_hi (FU)
Multiply and Multiply-Accumulate
to Accumulator
A0 = Dreg_lo_hi * Dreg_lo_hi (IS)
Multiply and Multiply-Accumulate
to Accumulator
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
A0 = Dreg_lo_hi * Dreg_lo_hi (W32)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Dreg
half
0 0
0 1
1 0
1 1
0xC003 0000— 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0xC003 063F
0 0 0 0 0 Dreg
0xC083 0000— 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1
0xC083 063F
0 0 0 0 0 Dreg
0xC103 0000— 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1
0xC103 063F
0 0 0 0 0 Dreg
0xC063 0000— 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1
0xC063 063F
0 0 0 0 0 Dreg
Instruction Opcodes
Bin
0 0 0 src_reg_
half 0 Dreg #
0 0 0 src_reg_
half 0 Dreg #
0 0 0 src_reg_
half 0 Dreg #
0 0 0 src_reg_
half 0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-69