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Register file reads occur in the DF2 pipeline stage (for operands).
Register file writes occur in the WB stage (for stores). The multipliers and
the video units are active in the EX1 stage, and the ALUs and shifter are
active in the EX2 stage. The accumulators are written at the end of the
EX2 stage.
The program sequencer also controls stalling and invalidating the instruc-
tions in the pipeline. Multi-cycle instruction stalls occur between the IF3
and DEC stages. DAG and sequencer stalls occur between the DEC and
AC stages. Computation and register file stalls occur between the DF2 and
EX1 stages. Data memory stalls occur between the EX1 and EX2 stages.
The sequencer ensures that the pipeline is fully interlocked and
that all the data hazards are hidden from the programmer.
Multi-cycle instructions behave as multiple single-cycle instructions being
issued from the decoder over several clock cycles. For example, the Push
Multiple or Pop Multiple instruction can push or pop from 1 to 14
DREGS and/or PREGS, and the instruction remains in the decode stage
for a number of clock cycles equal to the number of registers being
accessed.
Multi-issue instructions are 64 bits in length and consist of one 32-bit
instruction and two 16-bit instructions. All three instructions execute in
the same amount of time as the slowest of the three.
Any nonsequential program flow can potentially decrease the processor's
instruction throughput. Nonsequential program operations include:
• Jumps
• Subroutine calls and returns
• Interrupts and returns
• Loops
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Program Sequencer
4-9
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