Analog Devices ADSP-BF56x Blackfin Manuals

Manuals and User Guides for Analog Devices ADSP-BF56x Blackfin. We have 1 Analog Devices ADSP-BF56x Blackfin manual available for free PDF download: Reference

Analog Devices ADSP-BF56x Blackfin Reference

Analog Devices ADSP-BF56x Blackfin Reference (1042 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 5.25 MB

Table of Contents

Programming Reference
1
Copyright Information
2
Table of Contents
3
Preface

25
- Intended Audience
  25
- Purpose of this Manual
  25
- Manual Contents
  26
- What's New in this Manual
  27
- Technical or Customer Support
  28
- Product Information
  29
  - Myanalog.com
    30
  - Processor Product Information
    30
  - Related Documents
    31
  - Online Technical Documentation
    32
    
    Accessing Documentation from Visualdsp
    33
    
    Accessing Documentation from Windows
    33
    
    Accessing Documentation from the Web
    34
    
    Printed Manuals
    34
    
    Data Sheets
    35
    
    Hardware Tools Manuals
    35
    
    Processor Manuals
    35
    
    Visualdsp++ Documentation Set
    35
  - Conventions
    36
- Supported Processors
  29
Introduction

39
- Core Architecture
  39
- Memory Architecture
  42
  - Internal Memory
    43
  - External Memory
    44
  - I/O Memory Space
    44
- Event Handling
  44
  - Core Event Controller (CEC)
    46
  - System Interrupt Controller (SIC)
    46
- Syntax Conventions
  46
  - Case Sensitivity
    46
  - Free Format
    47
  - Instruction Delimiting
    47
  - Comments
    48
- Notation Conventions
  48
- Behavior Conventions
  50
- Glossary
  51
  - Register Names
    51
  - Functional Units
    52
  - Arithmetic Status Flags
    53
  - Fractional Convention
    54
  - Saturation
    55
  - Rounding and Truncating
    57
  - Automatic Circular Addressing
    59
Computational Units

61
- Using Data Formats
  64
  - Binary String
    64
  - Unsigned
    64
  - Signed Numbers: Two's-Complement
    65
  - Fractional Representation: 1.15
    65
- Register Files
  66
  - Data Register File
    67
  - Accumulator Registers
    68
  - Register File Instruction Summary
    69
- Data Types
  71
  - Endianess
    73
  - ALU Data Types
    74
  - Multiplier Data Types
    74
  - Shifter Data Types
    75
  - Arithmetic Formats Summary
    76
- Using Multiplier Integer and Fractional Formats
  77
- Rounding Multiplier Results
  79
  - Unbiased Rounding
    80
  - Biased Rounding
    82
  - Truncation
    83
- Special Rounding Instructions
  84
- Using Computational Status
  84
- ASTAT Register
  85
- Arithmetic Logic Unit (ALU)
  86
  - ALU Operations
    86
    
    Dual 16-Bit Operations
    87
    
    Single 16-Bit Operations
    87
    
    Quad 16-Bit Operations
    88
    
    Dual 32-Bit Operations
    89
    
    Single 32-Bit Operations
    89
  - ALU Instruction Summary
    90
  - ALU Division Support Features
    94
  - Special SIMD Video ALU Operations
    95
- Multiply Accumulators (Multipliers)
  95
  - Multiplier Operation
    96
    
    Placing Multiplier Results in Multiplier Accumulator Registers
    97
    
    Rounding or Saturating Multiplier Results
    97
  - Saturating Multiplier Results on Overflow
    98
    
    Multiplier Instruction Summary
    98
    
    Multiplier Instruction Options
    100
    
    Multiplier Data Flow Details
    102
    
    Multiply Without Accumulate
    104
    
    Special 32-Bit Integer MAC Instruction
    106
    
    Dual MAC Operations
    107
  - Barrel Shifter (Shifter)
    108
    
    Shifter Operations
    108
    
    Immediate Shifts
    109
    
    Two-Operand Shifts
    109
    
    Immediate Shifts
    110
    
    Register Shifts
    110
    
    Three-Operand Shifts
    110
    
    Register Shifts
    111
    
    Bit Test, Set, Clear, Toggle
    112
    
    Field Extract and Field Deposit
    112
    
    Shifter Instruction Summary
    113
Operating Modes and States

117
- Idle State
  118
- User Mode
  119
  - Protected Resources and Instructions
    120
  - Protected Memory
    121
  - Entering User Mode
    121
    
    Example Code to Enter User Mode Upon Reset
    121
    
    Return Instructions that Invoke User Mode
    121
- Supervisor Mode
  123
  - Non-OS Environments
    123
    
    Example Code for Supervisor Mode Coming out of Reset
    124
- Emulation Mode
  125
- Idle State
  125
  - Example Code for Transition to Idle State
    126
- Reset State
  126
- System Reset and Powerup
  128
  - Hardware Reset
    129
  - SYSCR Register
    130
  - Software Resets and Watchdog Timer
    130
  - SWRST Register
    131
  - Core-Only Software Reset
    132
  - Core and System Reset
    132
Program Sequencer

135
- Introduction
  135
  - Sequencer Related Registers
    139
- Instruction Pipeline
  141
- Branches
  144
  - Direct Short and Long Jumps
    145
  - Direct Call
    146
  - Indirect Branch and Call
    146
  - PC-Relative Indirect Branch and Call
    147
- Subroutines
  147
  - Stack Variables and Parameter Passing
    149
- Condition Code Flag
  152
  - Conditional Branches
    153
  - Conditional Register Move
    154
- Branch Prediction
  154
- Hardware Loops
  155
  - Two-Dimensional Loops
    158
  - Loop Unrolling
    160
  - Saving and Resuming Loops
    161
    
    Example Code for Using Hardware Loops in an ISR
    162
- Events and Interrupts
  163
  - System Interrupt Processing
    165
  - System Peripheral Interrupts
    167
  - SIC_IWR Register
    168
  - SIC_ISR Register
    170
  - SIC_IMASK Register
    170
  - System Interrupt Assignment Registers (Sic_Iarx)
    171
  - Core Event Controller Registers
    172
    
    IMASK Register
    172
    
    ILAT Register
    173
    
    IPEND Register
    174
  - Event Vector Table
    175
  - Return Registers and Instructions
    176
    
    Executing RTX, RTN, or RTE in a Lower Priority Event
    179
  - Emulation Interrupt
    179
  - Reset Interrupt
    180
  - NMI (Nonmaskable Interrupt)
    180
  - Exceptions
    181
  - Hardware Error Interrupt
    181
  - Core Timer Interrupt
    181
  - General-Purpose Interrupts (IVG7-IVG15)
    181
- Interrupt Processing
  182
  - Global Enabling/Disabling of Interrupts
    182
  - Servicing Interrupts
    182
  - Software Interrupts
    184
  - Nesting of Interrupts
    185
    
    Nested Interrupts
    185
    
    Non-Nested Interrupts
    185
    
    Example Epilog Code for Nested Interrupt Service Routine
    188
    
    Logging of Nested Interrupt Requests
    189
    
    Self-Nesting of Core Interrupts
    189
    
    Additional Usability Issues
    190
    
    Allocating the System Stack
    190
    
    Latency in Servicing Events
    190
  - Hardware Errors and Exception Handling
    192
    
    Hardware Error Interrupt
    193
    
    SEQSTAT Register
    193
    
    Exceptions
    195
    
    Exceptions While Executing an Exception Handler
    200
    
    Exceptions and the Pipeline
    201
    
    Deferring Exception Processing
    202
    
    Example Code for an Exception Handler
    202
    
    Example Code for an Exception Routine
    204
Address Arithmetic Unit

205
- Addressing with the AAU
  209
  - Pointer Register File
    210
    
    Frame and Stack Pointers
    210
  - DAG Register Set
    212
  - Indexed Addressing with Index & Pointer Registers
    212
    
    Loads with Zero or Sign Extension
    213
    
    Indexed Addressing with Immediate Offset
    214
  - Auto-Increment and Auto-Decrement Addressing
    214
  - Pre-Modify Stack Pointer Addressing
    215
  - Post-Modify Addressing
    215
  - Addressing Circular Buffers
    216
  - Addressing with Bit-Reversed Addresses
    219
- Modifying DAG and Pointer Registers
  219
- Memory Address Alignment
  220
- AAU Instruction Summary
  223
Memory

229
- Memory Architecture
  230
  - Overview of On-Chip Level 1 (L1) Memory
    230
Cache Control

232
- Prefetch
  232
  - Overview of Scratchpad Data SRAM
    232
  - Overview of On-Chip Level 2 (L2) Memory
    232
  - L1 Instruction Memory
    233
    
    IMEM_CONTROL Register
    233
- Flush
  234
  - L1 Instruction SRAM
    235
  - L1 Instruction Cache
    238
    
    Cache Lines
    238
    
    Cache Hits and Misses
    241
    
    Cache Line Fills
    242
    
    Cache Line Replacement
    243
    
    Line Fill Buffer
    243
    
    Instruction Cache Locking by Line
    244
    
    Instruction Cache Management
    244
    
    Instruction Cache Locking by Way
    245
    
    Instruction Cache Invalidation
    246
    
    ITEST_COMMAND Register
    249
- Instruction Test Registers
  250
  - ITEST_DATA1 Register
    250
  - ITEST_DATA0 Register
    251
- L1 Data Memory
  252
  - DMEM_CONTROL Register
    252
  - L1 Data SRAM
    255
  - L1 Data Cache
    257
    
    Example of Mapping Cacheable Address Space
    258
    
    Data Cache Access
    261
    
    Cache Write Method
    263
    
    IPRIO Register and Write Buffer Depth
    263
- Flushinv
  265
  - Data Cache Control Instructions
    265
  - Data Cache Invalidation
    266
- Data Test Registers
  266
  - DTEST_COMMAND Register
    267
  - DTEST_DATA1 Register
    269
  - DTEST_DATA0 Register
    270
- On-Chip Level 2 (L2) Memory
  271
  - On-Chip L2 Bank Access
    271
  - Latency
    272
- Memory Protection and Properties
  273
  - Memory Management Unit
    273
  - Memory Pages
    276
    
    Memory Page Attributes
    276
  - Page Descriptor Table
    278
  - CPLB Management
    278
  - MMU Application
    280
  - Examples of Protected Memory Regions
    282
  - Icplb_Datax Registers
    283
  - Dcplb_Datax Registers
    285
  - Dcplb_Addrx Registers
    287
  - Icplb_Addrx Registers
    288
  - DCPLB_STATUS and ICPLB_STATUS Registers
    289
  - DCPLB_FAULT_ADDR and ICPLB_FAULT_ADDR
    291
    
    Registers
    291
- Memory Transaction Model
  293
- Load/Store Operation
  294
  - Interlocked Pipeline
    294
  - Ordering of Loads and Stores
    295
  - Synchronizing Instructions
    296
  - Speculative Load Execution
    297
  - Conditional Load Behavior
    298
- Working with Memory
  299
  - Alignment
    299
  - Cache Coherency
    299
    
    Atomic Operations
    300
    
    Memory-Mapped Registers
    300
    
    Core MMR Programming Code Example
    301
  - Terminology
    302
Program Flow Control

305
- Jump
  306
- If CC Jump
  309
- Call
  312
- RTS, RTI, RTX, RTN, RTE (Return)
  313
- Lsetup, Loop
  317
Load / Store

325
- Load Immediate
  327
- Load Pointer Register
  331
- Load Data Register
  334
- Load Half-Word - Zero-Extended
  339
- Load Half-Word - Sign-Extended
  343
- Load High Data Register Half
  347
- Load Low Data Register Half
  351
- Load Byte - Zero-Extended
  355
- Load Byte - Sign-Extended
  358
- Store Pointer Register
  361
- Store Data Register
  364
- Store High Data Register Half
  369
- Store Low Data Register Half
  373
- Store Byte
  378
Move

382
- Move Register
  382
- Move Conditional
  388
- Move Half to Full Word - Zero-Extended
  390
- Move Half to Full Word - Sign-Extended
  393
- Move Register Half
  395
- Move Byte - Zero-Extended
  403
- Move Byte - Sign-Extended
  405
10 Stack Control

407
- SP (Push)
  407
  - Sp (Push)
    408
  - SP (Push Multiple)
    410
- SP (Push Multiple)
  411
- SP++ (Pop)
  414
- SP++ (Pop Multiple)
  417
- SP++ (Pop Multiple)
  418
- Link, Unlink
  423
Control Code Bit Management

427
- Compare Data Register
  427
- Compare Data Register
  428
- Compare Pointer
  431
- Compare Pointer
  432
- Compare Accumulator
  434
- Compare Accumulator
  435
- Move CC
  438
- Negate CC
  441
12 Logical Operations

443
- (And)
  443
- (NOT One's-Complement)
  446
- (Exclusive-OR)
  450
- Bxorshift, Bxor
  451
13 Bit Operations

459
- Bitclr
  460
- Bitset
  462
- Bittgl
  463
- Bittst
  466
- Deposit
  468
- Extract
  473
- Bitmux
  479
- Ones (One's-Population Count)
  484
14 Shift/Rotate Operations

487
- Add with Shift
  487
- Add with Shift
  488
- Shift with Add
  490
- Shift with Add
  491
- Arithmetic Shift
  493
- Logical Shift
  499
- Logical Shift
  500
- ROT (Rotate)
  506
Arithmetic Operations

516
- Abs
  516
- Add
  518
- Add/Subtract - Prescale down
  522
- Add/Subtract - Prescale up
  524
- Add Immediate
  528
- DIVS, DIVQ (Divide Primitive)
  531
- Expadj
  541
- Max
  542
- Min
  544
- Modify - Decrement
  546
- Modify - Increment
  549
- Multiply 16-Bit Operands
  555
- Multiply 32-Bit Operands
  563
- Multiply and Multiply-Accumulate to Accumulator
  565
- Multiply and Multiply-Accumulate to Half-Register
  570
- Multiply and Multiply-Accumulate to Data Register
  579
- Negate (Two's-Complement)
  585
- RND (Round to Half-Word)
  589
- Saturate
  592
- Signbits
  595
- Subtract
  598
- Subtract Immediate
  602
External Event Management

607
- Idle
  607
- Core Synchronize
  609
- System Synchronize
  612
- Emuexcpt (Force Emulation)
  615
- Disable Interrupts
  617
- Enable Interrupts
  619
- Raise (Force Interrupt / Reset)
  621
- Excpt (Force Exception)
  624
- Test and Set Byte (Atomic)
  626
- No Op
  629
- Iflush
  631
- Align8, Align16, Align24
  643
- Disalgnexcpt
  646
- Byteop3P (Dual 16-Bit Add / Clip)
  648
- Dual 16-Bit Accumulator Extraction with Addition
  653
- Byteop16P (Quad 8-Bit Add)
  655
- Byteop1P (Quad 8-Bit Average – Byte)
  659
- Byteop2P (Quad 8-Bit Average – Half-Word)
  664
- Bytepack (Quad 8-Bit Pack)
  670
- Byteop16M (Quad 8-Bit Subtract)
  672
- Saa (Quad 8-Bit Subtract-Absolute-Accumulate)
  676
- Byteunpack (Quad 8-Bit Unpack)
  681
Vector Operations

691
- Add on Sign
  691
- Vit_Max (Compare-Select)
  696
- Vector ABS
  703
- Vector Add / Subtract
  706
- Vector Arithmetic Shift
  711
- Vector Logical Shift
  716
- Vector MAX
  720
- Vector MIN
  723
- Vector Multiply
  726
- Vector Multiply and Multiply-Accumulate
  729
- Vector Negate (Two's-Complement)
  734
- Vector PACK
  736
- Vector SEARCH
  738
Issuing Parallel Instructions

743
- Supported Parallel Combinations
  743
- Parallel Issue Syntax
  744
- Bit ALU/MAC Instructions
  745
  - Bit Instructions
    748
  - Examples
    750
  - Watchpoint Unit
    753
  - Instruction Watchpoints
    756
  - Wpian Registers
    757
  - Wpiacntn Registers
    758
  - WPIACTL Register
    759
  - Data Address Watchpoints
    762
  - Wpdan Registers
    762
  - Wpdacntn Registers
    763
  - WPDACTL Register
    764
  - WPSTAT Register
    766
  - Trace Unit
    767
  - TBUFCTL Register
    768
  - TBUFSTAT Register
    769
  - TBUF Register
    770
  - Code to Recreate the Execution Trace in Memory
    770
  - Performance Monitoring Unit
    771
  - Pfcntrn Registers
    772
  - PFCTL Register
    772
  - Event Monitor Table
    773
  - Instruction Opcodes
    801
  - Move Instructions
    828

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