Instruction Cache Locking By Way - Analog Devices ADSP-BF53x Blackfin Reference

cacheable line is fetched. This bit indicates that a line is of either "low" or
"high" importance. In a modified LRU policy, a high can replace a low,
but a low cannot replace a high. If all Ways are occupied by highs, an oth-
erwise cacheable low will still be fetched for the core, but will not be
cached. Fetched highs seek to replace unoccupied Ways first, then least
recently used lows next, and finally other highs using the LRU policy.
Lows can only replace unoccupied Ways or other lows, and do so using
the LRU policy. If all previously cached highs ever become less important,
they may be simultaneously transformed into lows by writing to the
bit in the
PRIRST

Instruction Cache Locking by Way

The instruction cache has four independent lock bits (
control each of the four Ways of the instruction cache. When the cache is
enabled, L1 Instruction Memory has four Ways available. Setting the lock
bit for a specific Way prevents that Way from participating in the LRU
replacement policy. Thus, a cached instruction with its Way locked can
only be removed using an
assisted manipulation of the tag array.
An example sequence is provided below to demonstrate how to lock down
Way0:
• If the code of interest may already reside in the instruction cache,
invalidate the entire cache first (for an example, see
Cache Invalidation" on page
• Disable interrupts, if required, to prevent interrupt service routines
(ISRs) from potentially corrupting the locked cache.
• Set the locks for the other Ways of the cache by setting
Only Way0 of the instruction cache can now be replaced by new
code.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
register (see
IMEM_CONTROL
instruction, or a "back door" MMR
IFLUSH
page 6-5).
6-18).
Memory
LRU-
]) that
ILOC[3:0
"Instruction
ILOC[3:1]
6-17
.