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L1 Instruction Memory
Write access to the L1 Instruction SRAM Memory must be made through
the 64-bit wide system DMA port. Because the SRAM is implemented as a
collection of single ported subbanks, the instruction memory is effectively
dual ported.
Figure 6-3 on page 6-9
tion Memory. As the figure shows, each 16K byte bank is made up of four
4K byte subbanks. In the figure, dotted lines indicate features that exist
only on some Blackfin processors. Please refer to the hardware reference
manual for your particular processor for more details.
While on some processors the EAB and DCB buses shown in
connect directly to the EBIU and DMA controllers, on derivatives that
feature multiple cores or on-chip L2 memories they must cross additional
arbitration units. Also, these buses are wider than 16 bits on some parts.
For details, refer to the specific Blackfin Processor Hardware Reference man-
ual for your derivative.
6-8
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
describes the bank architecture of the L1 Instruc-
Figure 6-3
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