Analog Devices ADSP-BF53x Blackfin Reference page 186

Interrupt Processing
CYCLE: 1
IF 1
A9 A1 0
IF 2 A8 A9
A7 A8
IF 3
A6
DEC A7
A5 A6
AC
DF1 A4 A5
DF2 A3 A4
EX1
A2
A3
EX2 A1 A2
WB A0 A1
CYCLE 1: INTERRUPT IS LATCHED. ALL POSSIBLE INTERRUPT SOURCES DETERMINED.
CYCLE 2: INTERRUPT IS PRIORITIZED.
CYCLE 3: ALL INSTRUCTIONS ABOVE A2 ARE KILLED. A2 IS KILLED IF IT IS AN RTI OR CLI
INSTRUCTION. ISR STARTING ADDRESS LOOKUP OCCURS.
CYCLE 4: I0 (INSTRUCTION AT START OF ISR) ENTERS PIPELINE.
CYCLE M: WHEN THE RTI INSTRUCTION REACHES THE DF1 STAGE, INSTRUCTION A3 IS
FETCHED IN PREPARATION FOR RETURNING FROM INTERRUPT.
CYCLE M+4: RTI HAS REACHED WB STAGE, RE-ENABLING INTERRUPTS.
Figure 4-8. Non-nested Interrupt Handling
Supervisor stack. Processor state is stored in the Supervisor stack, not in
the User stack. Hence, the instructions to push
pop (
RETI RETI = [SP++]
4-52 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
INTERRUPTS DISABLED
DURING THIS INTERVAL.
2
3 4 5 6
I0 I1 I2
I0 I1
A1 0
I0
A9
A8
A7
A6
A5
A4
A3
A2
) use the Supervisor stack.
m m+1 m+2 m+3
. . . A4 A5 A6
A3
. . .
A3 A4 A5
. . .
A3 A4
. . .
A3
. . .
RTI
. . .
. . . I n
RTI
I n-1
. . . RTI
I n-1
I n-2 RTI
I n
. . .
. . . I n-3 I n-2 I n-1 I n
(
RETI
m+4
A7
A6
A5
A4
A3
RTI
) and
[--SP] = RETI