Load/Store Operation; Interlocked Pipeline - Analog Devices ADSP-BF53x Blackfin Reference

Load/Store Operation

Load/Store Operation
The Blackfin processor architecture supports the RISC concept of a
Load/Store machine. This machine is the characteristic in RISC architec-
tures whereby memory operations (loads and stores) are intentionally
separated from the arithmetic functions that use the targets of the memory
operations. The separation is made because memory operations, particu-
larly instructions that access off-chip memory or I/O devices, often take
multiple cycles to complete and would normally halt the processor, pre-
venting an instruction execution rate of one instruction per cycle.
In write operations, the store instruction is considered complete as soon as
it executes, even though many cycles may execute before the data is actu-
ally written to an external memory or I/O location. This arrangement
allows the processor to execute one instruction per clock cycle, and it
implies that the synchronization between when writes complete and when
subsequent instructions execute is not guaranteed. Moreover, this syn-
chronization is considered unimportant in the context of most memory
operations.

Interlocked Pipeline

In the execution of instructions, the Blackfin processor architecture imple-
ments an interlocked pipeline. When a load instruction executes, the
target register of the read operation is marked as busy until the value is
returned from the memory system. If a subsequent instruction tries to
access this register before the new value is present, the pipeline will stall
until the memory operation completes. This stall guarantees that instruc-
tions that require the use of data resulting from the load do not use the
previous or invalid data in the register, even though instructions are
allowed to start execution before the memory read completes.
This mechanism allows the execution of independent instructions between
the load and the instructions that use the read target without requiring the
programmer or compiler to know how many cycles are actually needed for
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