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Options
The Store Low Data Register Half instruction supports the following
options.
• Post-increment the destination pointer by 2 bytes.
• Post-decrement the destination pointer by 2 bytes.
• Offset the source pointer with a small (5-bit), half-word-aligned
(even), unsigned constant.
• Offset the source pointer with a large (17-bit), half-word-aligned
(even), signed constant.
Indirect and Post-Increment Index Addressing
The syntax of the form:
[Dst_1 ++ Dst_2] = Src
is indirect, post-increment index addressing. The form is shorthand for
the following sequence.
[Dst_1] = Src_lo ;
ter, indirect*/
Dst_1 += Dst_2 ;
by Dst_2 */
where:
•
is the least significant half of the source register. (
Src
Dreg_lo
•
is the memory destination pointer register on the left side of
Dst_1
the syntax.
•
is the increment index register.
Dst_2
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* store the lower half of the source regis-
/* post-increment Dst_1 by a quantity indexed
in the syntax example).
Load / Store
or
Dreg
8-51
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