Analog Devices ADSP-BF53x Blackfin Reference page 376

Instruction Overview
Indirect and post-increment index addressing supports customized indi-
rect address cadence. The indirect, post-increment index version must
have separate P-registers for the input operands. If a common
for the inputs, the auto-increment feature does not work.
Flags Affected
None
Required Mode
User & Supervisor
Parallel Issue
The 16-bit versions of this instruction can be issued in parallel with spe-
cific other instructions.
Instructions" on page 20-1.
The 32-bit versions of this instruction cannot be issued in parallel with
other instructions.
Example
w [ i1 ] = r3.l ;
w [ p0 ] = r3 ;
w [ i3 ++ ] = r7.l ;
w [ i0 -- ] = r1.l ;
w [ p4 ] = r2.l ;
w [ p1 ++ ] = r7 ;
w [ sp -- ] = r2 ;
w [ p2 + 12 ] = r6 ;
w [ p4 - 0x200C ] = r0 ;
w [ p2 ++ p0 ] = r5.l ;
8-52 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
For more information, see "Issuing Parallel
is used
Preg