Table of Contents
Advertisement
Functional Description
The Zero-Overhead Loop Setup instruction provides a flexible,
counter-based, hardware loop mechanism that provides efficient,
zero-overhead software loops. In this context, zero-overhead means that
the software in the loops does not incur a performance or code size penalty
by decrementing a counter, evaluating a loop condition, then calculating
and branching to a new target address.
When the
the
LSETUP
Begin_Loop
LSETUP
entry only.
The architecture includes two sets of three registers each to support two
independent, nestable loops. The registers are
Loop_Bottom (LBn)
describe
LC0
Loop0
The
and
LOOP
LSETUP
three registers in a single instruction. The size of the
instructions only supports a finite number of bits, so the loop range is lim-
ited. However,
initialized manually using Move instructions if loop length and repetition
count need to be beyond the limits supported by the
tax. Thus, a single loop can span the entire 4 GB of memory space.
When initializing
ually, make sure that
configured before setting
count value.
The instruction syntax supports an optional initialization value from a
P-register or P-register divided by 2.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
address is the next sequential address after
Begin_Loop
instruction, the loop has zero overhead. If the
address is not the next sequential address after the
instruction, there is some overhead that is incurred on loop
and
Loop_Count (LCn)
, and
,
, and
LT1
LB1
instructions are a convenient way to initialize all
and
,
LT0
LT1
LB0
and
LT0
Loop_Top
Program Flow Control
Loop_Top (LTn)
. Consequently,
describe
LC1
and
and
and
LB1
LC0
,
and
, and
LT1
LB0
LB1
(
) and
LTn
Loop_Bottom
(
) to the desired loop
Loop_Count
LCn
,
,
, and
LT0
LB0
.
Loop1
and
LOOP
LSETUP
can be
LC1
and
LOOP
LSETUP
and
man-
LC0
LC1
(
) are
LBn
syn-
7-15
Advertisement
Table of Contents
