Flush - Analog Devices ADSP-BF53x Blackfin Reference

L1 Instruction Memory
nonparticipating Ways. Code in nonparticipating Ways can still be
removed from the cache using an
is 0, the corresponding Way is not locked and that Way participates in
cache replacement policy. If an
is locked and does not participate in cache replacement policy.
The bit reserves a portion of L1 instruction SRAM to serve as cache.
IMC
Note reserving memory to serve as cache will not alone enable L2 memory
accesses to be cached. CPLBs must also be enabled using the
and the CPLB descriptors (
specify desired memory pages as cache-enabled.
Instruction CPLBs are disabled by default after reset. When disabled, only
minimal address checking is performed by the L1 memory interface. This
minimal checking generates an exception to the processor whenever it
attempts to fetch an instruction from:
• Reserved (nonpopulated) L1 instruction memory space
• L1 data memory space
• MMR space
CPLBs must be disabled using this bit prior to updating their descriptors
( and
DCPLB_DATAx
weak (see "Ordering of Loads and Stores" on page
CPLBs should be proceeded by a
When enabling or disabling cache or CPLBs, immediately follow
the write to
To ensure proper behavior and future compatibility, all reserved
bits in this register must be set to 0 whenever this register is
written.
6-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
IFLUSH
ILOC[3:0]
ICPLB_DATAx
registers). Note since load store ordering is
DCPLB_ADDRx
CSYNC
with a
IMEM_CONTROL
instruction. If an
bit is 1, the corresponding Way
and
ICPLB_ADDRx
6-67), disabling of
.
to ensure proper behavior.
SSYNC
bit
ILOC[3:0]
bit
EN_ICPLB
registers) must