Analog Devices ADSP-BF53x Blackfin Reference page 138

Introduction
PERIPHERALS
SCLK
CCLK
CORE EVENT CONTROLLER
PROGRAM SEQUENCER
SYSCFG
SEQSTAT
CYCLES
CYCLES2
INSTRUCTION
DECODER
Figure 4-2. Program Sequencing and Interrupt Processing Block Diagram
4-4 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
SYSTEM INTERRUPT CONTROLLER
SIC_IAR0
SIC_IAR1
SIC_IAR2
SIC_IAR3
LC0 LT0 LB0
RETS
LC1 LT1 LB1
RETI
RETX
RETN
RETE
LOOP
COMPARATORS
JTAG TEST
DEBUG
AND
EMULATION
SIC_ISR
SIC_IWR
SIC_IMASK
ILAT
IMASK
IPEND
PROGRAM
COUNTER
FETCH
COUNTER
ALIGNMENT
UNIT
LOOP
BUFFERS
DYNAMIC
POWER
MANAGEMENT
PAB 16/32
EMULATION
RESET
NMI
EXCEPTIONS
HARDWARE ERRORS
CORE TIMER
RAB 32
PREG 32
ADDRESS
ARITHMETIC
UNIT
32
IAB
L1
INSTRUCTION
MEMORY
IDB 64