Analog Devices ADSP-BF53x Blackfin Reference page 649

as bytes on half-word boundaries in one 32-bit destination register. Some
syntax options load the upper byte in the half-word and others load the
lower byte, as shown in
Table 18-2. Assuming the source registers contain:
aligned_src_reg_0:
aligned_src_reg_1:
Table 18-3. The versions that load the result into the lower byte–"(LO)"–
produce:
dest_reg:
Table 18-4. And the versions that load the result into the higher byte–
"(HI)"–produce:
dest_reg:
In either case, the unused bytes in the destination register are filled with
0x00.
The 8-bit and 16-bit addition is performed as a signed operation. The
16-bit operand is sign-extended to 32 bits before adding.
The only valid input source register pairs are
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Table 18-2,
31................24 23................16
y1
z3
31................24 23................16
0 . . . . . 0 y1 + z3 clipped
31................24 23................16
y1 + z2 clipped
to 8 bits
Video Pixel Operations
Table 18-4, and
15..................8
z2 z1
15..................8
0 . . . . . 0
to 8 bits
15..................8
0 . . . . .0 y0 + z0 clipped
to 8 bits
and
R1:0
Table 18-4.
7....................0
y0
z0
7....................0
y0 + z1 clipped
to 8 bits
7....................0
0 . . . . .0
.
R3:2
18-9