Flags Affected
None
Required Mode
User & Supervisor
Parallel Issue
The
instruction cannot be issued in parallel with other instructions.
SSYNC
Example
Consider the following example code sequence.
if cc jump away_from_here ;
prediction */
ssync ;
r0 = [p0] ;
In this example,
cuted speculatively. The instruction ensures that the conditional branch is
resolved and any entries in the processor store buffer and write buffer have
been flushed. In addition, all exceptions complete processing before
completes.
Also See
Core
Synchronize,
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* load */
ensures that the load instruction will not be exe-
SSYNC
Idle
External Event Management
/* produces speculative branch
SSYNC
16-9
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