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Data Test Registers
DTEST_DATA0 Register
The Data Test Data 0 register (
the 64-bit data to be written, or it contains the lower 32 bits of the desti-
nation for the 64-bit data read. The
access the tag arrays and contains the Valid and Dirty bits, which indicate
the state of the cache line.
Data Test Data 0 Register (DTEST_DATA0)
0xFFE0 0400
Used to access the L1 cache tag arrays. The address tag consists of the upper 18 bits
and bit 11 of the physical address. See
Tag[3:2]
Physical address
Tag
Physical address
LRU
0 - Way0 is the least
recently used
1 - Way1 is the least
recently used
Figure 6-15. Data Test Data 0 Register
6-42
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
DTEST_DATA0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10 9
8
X
X
X
X
X
X
X
X
"Cache Lines" on page
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11
10
9
8
X
X
X
X
X
X
X
X
) stores the lower 32 bits of
register is also used to
DTEST_DATA0
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
6-10.
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
Reset = Undefined
Data[31:16]
Data[15:0]
Reset = Undefined
Tag[19:4]
Physical address
Valid
0 - Cache line invalid
1 - Cache line valid
Dirty
0 - Cache line unmodified
since it was copied from
source memory
1 - Cache line modified
after it was copied
from source memory
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