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Performance Monitoring Unit
PFCNTRn Registers
Figure 21-12
shows the Performance Monitor Counter registers,
. The
PFCNTR[1:0]
mance counter 0. The
performance counter 1.
Performance Monitor Counter Registers (PFCNTRn)
PRCNTR0:
0xFFE0 8100
PRCNTR1:
0xFFE0 8104
PFCNTRx[31:16]
PFCNTRx[15:0]
Figure 21-12. Performance Monitor Counter Registers
PFCTL Register
To enable the Performance Monitoring Unit, set the
formance Monitor Control register (
the unit is enabled, individual count-enable bits (
the
bits to enable or disable the performance monitors in User
PFCENx
mode, Supervisor mode, or both. Use the
event triggered.
21-20
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
register contains the count value of perfor-
PFCNTR0
register contains the count value of
PFCNTR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PFPWR
), shown in
Figure
PFCTL
PFCENn
bits to select the type of
PEMUSWx
Reset = Undefined
bit in the Per-
21-13. Once
) take effect. Use
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