Reset Interrupt; Nmi (Nonmaskable Interrupt) - Analog Devices ADSP-BF53x Blackfin Reference

Events and Interrupts

Reset Interrupt

The reset interrupt (
expiration of the watchdog timer. This location differs from that of other
interrupts in that its content is read-only. Writes to this address change
the register but do not change where the processor vectors upon reset. The
processor always vectors to the reset vector address upon reset. For more
information, see
The core has an output that indicates that a double fault has occurred.
This is a nonrecoverable state. The system (via the
programmed to send a reset request if a double fault condition is detected.
Subsequently, the reset request forces a system reset for core and
peripherals.
The reset vector is determined by the processor system. It points to the
start of the on-chip boot ROM, or to the start of external asynchronous
memory, depending on the state of the

NMI (Nonmaskable Interrupt)

The NMI entry is reserved for a nonmaskable interrupt, which can be gen-
erated by the Watchdog timer or by the NMI input signal to the
processor. An example of an event that requires immediate processor
attention, and thus is appropriate as an NMI, is a powerdown warning.
If an exception occurs in an event handler that is already servicing
an Exception,
double fault condition, and the address of the excepting instruction
will be written to
If unused, the
some derivatives, the
Please refer to the specific data sheet for your processor.
4-46 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) can be initiated via the
RST
"Reset State" on page
, Reset, or Emulation event, this will trigger a
NMI
.
RETX
pin should always be pulled to its deasserted state. On
NMI
input is active high and on some it is active low.
NMI
pin or through
RESET
3-10.
SWRST
pins.
BMODE
register) can be