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The address tag consists of the upper 18 bits plus bits 11 and 10 of the
physical address. Bits 12 and 13 of the physical address are not part of the
address tag. Instead, these bits are used to identify the 4K byte memory
subbank targeted for the access.
The LRU bits are part of an LRU algorithm used to determine which
cache line should be replaced if a cache miss occurs.
The Valid bit indicates the state of a cache line. A cache line is always
valid or invalid.
• Invalid cache lines have their Valid bit cleared, indicating the line
will be ignored during an address-tag compare operation.
• Valid cache lines have their Valid bit set, indicating the line con-
tains valid instruction/data that is consistent with the source
memory.
The tag and data components of a cache line are illustrated in
Each 4K byte subbank provides the same structure.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Memory
Figure
6-5.
6-11
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