Multiplier Data Flow Details - Analog Devices ADSP-BF53x Blackfin Reference

Multiply Accumulators (Multipliers)

Multiplier Data Flow Details

Figure 2-10 shows the Register files and ALUs, along with the multiplier/
accumulators.
TO MEMORY
R0
R1
R2
R3
R4
R5
R6
R7
FROM MEMORY
Figure 2-10. Register Files and ALUs
Each multiplier has two 16-bit inputs, performs a 16-bit multiplication,
and stores the result in a 40-bit accumulator or extracts to a 16-bit or
32-bit register. Two 32-bit words are available at the MAC inputs, provid-
ing four 16-bit operands to chose from.
One of the operands must be selected from the low half or the high half of
one 32-bit word. The other operand must be selected from the low half or
the high half of the other 32-bit word. Thus, each MAC is presented with
four possible input operand combinations. The two 32-bit words can
2-42 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
32b
R0.H R0.L
R1.H R1.L
R2.H R2.L
R3.H R3.L
R4.H R4.L
R5.H R5.L
R6.H R6.L
R7.H R7.L
32b
ALUs
32b
32b
OPERAND OPERAND
SELECTION SELECTION
MAC0
MAC1
A1 A0
SHIFTER
32b