Analog Devices ADSP-BF53x Blackfin Reference page 903

Table C-20. Video Pixel Operations Instructions (Sheet 2 of 5)
Instruction
and Version
Dual 16-Bit Add / Clip
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO, R)
Dual 16-Bit Add / Clip
NOTE: When issuing compatible load/store instructions in parallel with a Dual 16-Bit Add / Clip
instruction, add 0x0800 0000 to the Dual 16-Bit Add / Clip opcode.
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI, R)
Dual 16-Bit Accumulator Extrac-
tion with Addition
NOTE: When issuing compatible load/store instructions in parallel with a Dual 16-Bit Accumulator
Extraction with Addition instruction, add 0x0800 0000 to the Dual 16-Bit Accumulator Extraction with
Addition opcode.
Dreg = A1.L + A1.H, Dreg = A0.L + A0.H
Quad 8-Bit Add
(Dreg, Dreg) = BYTEOP16P (Dreg_pair, Dreg_pair)
Quad 8-Bit Add
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Add instruction,
add 0x0800 0000 to the Quad 8-Bit Add opcode.
(Dreg, Dreg) = BYTEOP16P (Dreg_pair, Dreg_pair) (R)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC417 2000— 1 1 0 0 0 1 0 x x x 0 1 0 1 1 1
0xC417 1E3F
0 0 1 0 Dest. 0
0xC437 2000— 1 1 0 0 0 1 0 x x x 1 1 0 1 1 1
0xC437 1E3F
0 0 1 0 Dest. 0
0xC40C 403F— 1 1 0 0 0 1 0 x x x 0 0 1 1 0 0
0xC40C 4FC0
0 1 0 0 Dest. of
0xC415 0000— 1 1 0 0 0 1 0 x x x 0 1 0 1 0 1
0xC415 0FFF
0 0 0 0 Dest. 1
0xC415 2000— 1 1 0 0 0 1 0 x x x 0 1 0 1 0 1
0xC415 2FFF
0 0 1 0 Dest. 1
Instruction Opcodes
Bin
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
Dest of 1 1 1 1 1 1
A1 Op A0 Op
Dreg # Dreg #
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
C-103