Analog Devices ADSP-BF53x Blackfin Reference page 791

B CORE MMR ASSIGNMENTS
The Blackfin processor's memory-mapped registers (MMRs) are in the
address range 0xFFE0 0000 – 0xFFFF FFFF.
All core MMRs must be accessed with a 32-bit read or write access.
This appendix lists core MMR addresses and register names. To find more
information about an MMR, refer to the page shown in the "See Section"
column. When viewing the PDF version of this document, click a refer-
ence in the "See Section" column to jump to additional information about
the MMR.
L1 Data Memory Controller Registers
L1 Data Memory Controller registers (0xFFE0 0000 – 0xFFE0 0404)
Table B-1. L1 Data Memory Controller Registers
Memory-mapped
Address
0xFFE0 0004
0xFFE0 0008
0xFFE0 000C
0xFFE0 0100
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Register Name
DMEM_CONTROL
DCPLB_STATUS
DCPLB_FAULT_ADDR
DCPLB_ADDR0
See Section
"DMEM_CONTROL Register" on
page 6-24
"DCPLB_STATUS and ICPLB_STATUS
Registers" on page 6-61
"DCPLB_FAULT_ADDR and
ICPLB_FAULT_ADDR Registers" on
page 6-63
"DCPLB_ADDRx Registers" on page 6-59
B-1