Analog Devices ADSP-BF53x Blackfin Reference page 883

Table C-17. Arithmetic Operations Instructions (Sheet 29 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (TFU, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (S2RND, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (ISS2, M)
Multiply and Multiply-Accumulate
to Half Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (IH, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (FU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (IS)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC0D5 1800— 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1
0xC0D5 D9FF
Dreg
half
0xC035 1800— 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1
0xC035 D9FF
Dreg
half
0xC135 1800— 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1
0xC135 D9FF
Dreg
half
0xC175 1800— 1 1 0 0 0 0 0 1 0 1 1 1 0 1 0 1
0xC175 D9FF
Dreg
half
0xC006 1800— 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0xC006 D9FF
Dreg
half
0xC086 1800— 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0
0xC086 D9FF
Dreg
half
0xC106 1800— 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0
0xC106 D9FF
Dreg
half
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
C-83