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Table C-17. Arithmetic Operations Instructions (Sheet 27 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (FU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (IS)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (IU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (T)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (TFU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (S2RND)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC005 1800—
1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1
0xC005 D9FF
Dreg
half
0xC085 1800—
1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1
0xC085 D9FF
Dreg
half
0xC105 1800—
1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1
0xC105 D9FF
Dreg
half
0xC185 1800—
1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1
0xC185 D9FF
Dreg
half
0xC045 1800—
1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1
0xC045 D9FF
Dreg
half
0xC0C5 1800—
1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1
0xC0C5 D9FF
Dreg
half
0xC025 1800—
1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1
0xC025 D9FF
Dreg
half
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
C-81
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