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Instruction Overview
SAA (Quad 8-Bit Subtract-Absolute-Accumulate)
General Form
SAA ( src_reg_0, src_reg_1 )
SAA ( src_reg_0, src_reg_1 ) (R)
Syntax
SAA (Dreg_pair, Dreg_pair) ;
(b) */
SAA (Dreg_pair, Dreg_pair) (R) ;
ands (b) */
Syntax Terminology
:
Dreg_pair
R1:0
and
.)
R3:2
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Quad 8-Bit Subtract-Absolute-Accumulate instruction subtracts four
pairs of values, takes the absolute value of each difference, and accumu-
lates each result into a 16-bit Accumulator half. The results are placed in
the upper- and lower-half Accumulators
Saturation is performed if an operation overflows a 16-bit Accumulator
half.
Only register pairs
This instruction supports the following byte-wise Sum of Absolute Differ-
ence (SAD) calculations.
18-36
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
(This instruction only supports register pairs
R3:2
and
are valid sources for this instruction.
R1:0
R3:2
/* forward byte order operands
/* reverse byte order oper-
,
,
A0.H
A0.L
A1.H
R1:0
, and
.
A1.L
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