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Memory Protection and Properties
Page Descriptor Table
For memory accesses to utilize the cache when CPLBs are enabled for
instruction access, data access, or both, a valid CPLB entry must be avail-
able in an MMR pair. The MMR storage locations for CPLB entries are
limited to 16 descriptors for instruction fetches and 16 descriptors for
data load and store operations.
For small and/or simple memory models, it may be possible to define a set
of CPLB descriptors that fit into these 32 entries, cover the entire address-
able space, and never need to be replaced. This type of definition is
referred to as a static memory management model.
However, operating environments commonly define more CPLB descrip-
tors to cover the addressable memory and I/O spaces than will fit into the
available on-chip CPLB MMRs. When this happens, a memory-based
data structure, called a Page Descriptor Table, is used; in it can be stored
all the potentially required CPLB descriptors. The specific format for the
Page Descriptor Table is not defined as part of the Blackfin processor
architecture. Different operating systems, which have different memory
management models, can implement Page Descriptor Table structures
that are consistent with the OS requirements. This allows adjustments to
be made between the level of protection afforded versus the performance
attributes of the memory-management support routines.
CPLB Management
When the Blackfin processor issues a memory operation for which no
valid CPLB (cacheability protection lookaside buffer) descriptor exists in
an MMR pair, an exception occurs. This exception places the processor
into Supervisor mode and vectors to the MMU exception handler (see
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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