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Memory Protection and Properties
A single instruction may generate an instruction fetch as well as one or
two data accesses. It is possible that more than one of these memory oper-
ations references data for which there is no valid CPLB descriptor in an
MMR pair. In this case, the exceptions are prioritized and serviced in this
order:
• Instruction page miss
• A page miss on DAG0
• A page miss on DAG1
MMU Application
Memory management is an optional feature in the Blackfin processor
architecture. Its use is predicated on the system requirements of a given
application. Upon reset, all CPLBs are disabled, and the Memory Man-
agement Unit (MMU) is not used.
The MMU does not support automatic address translation in
hardware.
If all L1 memory is configured as SRAM, then the data and instruction
MMU functions are optional, depending on the application's need for
protection of memory spaces either between tasks or between User and
Supervisor modes. To protect memory between tasks, the operating sys-
tem can maintain separate tables of instruction and/or data memory pages
available for each task and make those pages visible only when the relevant
task is running. When a task switch occurs, the operating system can
ensure the invalidation of any CPLB descriptors on chip that should not
be available to the new task. It can also preload descriptors appropriate to
the new task.
For many operating systems, the application program is run in User mode
while the operating system and its services run in Supervisor mode. It is
desirable to protect code and data structures used by the operating system
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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