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Note when single-stepping through instructions in a debug environment,
the
register increases in non-unity increments due to the interac-
CYCLES
tion of the debugger over JTAG.
The
CYCLES
instead system registers.
Execution Cycle Count Registers (CYCLES and CYCLES2)
RO in User mode, RW in Supervisor and Emulator modes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
CYCLES / CYCLES2[31:16]
15 14 13 12 11 10
X
CYCLES / CYCLES2[15:0]
Figure 21-14. Execution Cycle Count Registers
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and
registers are not system MMRs, but are
CYCLES2
X
X
X
X
X
X
X
X
9
8
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6
4
3
2
1
0
X
X
X
X
X
X
X
Debug
Reset = Undefined
21-25
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