Analog Devices ADSP-BF53x Blackfin Reference page 985

Table C-23. 32-Bit Opcode Instructions (Sheet 32 of 40)
Instruction
and Version
Arithmetic Shift
Dreg_lo = ASHIFT Dreg_hi BY Dreg_lo (S)
Arithmetic Shift
Dreg_hi = ASHIFT Dreg_lo BY Dreg_lo (S)
Arithmetic Shift
Dreg_hi = ASHIFT Dreg_hi BY Dreg_lo (S)
Logical Shift
Dreg_lo = LSHIFT Dreg_lo BY Dreg_lo
Logical Shift
Dreg_lo = LSHIFT Dreg_hi BY Dreg_lo
Logical Shift
Dreg_hi = LSHIFT Dreg_lo BY Dreg_lo
Logical Shift
Dreg_hi = LSHIFT Dreg_hi BY Dreg_lo
Vector Arithmetic Shift
Dreg = ASHIFT Dreg BY Dreg_lo (V)
Vector Arithmetic Shift
Dreg = ASHIFT Dreg BY Dreg_lo (V, S)
Vector Logical Shift
Dreg = LSHIFT Dreg BY Dreg_lo (V)
Arithmetic Shift
Dreg = ASHIFT Dreg BY Dreg_lo
Arithmetic Shift
Dreg = ASHIFT Dreg BY Dreg_lo (S)
Logical Shift
Dreg = LSHIFT Dreg BY Dreg_lo
Rotate
Dreg = ROT Dreg BY Dreg_lo
Arithmetic Shift
A0 = ASHIFT A0 BY Dreg_lo
Arithmetic Shift
A1 = ASHIFT A1 BY Dreg_lo
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC600 5000—
0xC600 5E3F
0xC600 6000—
0xC600 6E3F
0xC600 7000—
0xC600 7E3F
0xC600 8000—
0xC600 8E3F
0xC600 9000—
0xC600 9E3F
0xC600 A000—
0xC600 AE3F
0xC600 B000—
0xC600 BE3F
0xC601 0000—
0xC601 0E3F
0xC601 4000—
0xC601 4E3F
0xC601 8000—
0xC601 8E3F
0xC602 0000—
0xC602 0E3F
0xC602 4000—
0xC602 4E3F
0xC602 8000—
0xC602 8E3F
0xC602 C000—
0xC602 CE3F
0xC603 0000—
0xC603 0038
0xC603 1000—
0xC603 1038
C-185