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Dual MAC Operations
The processor has two 16-bit MACs. Both MACs can be used in the same
operation to double the MAC throughput. The same two 32-bit input
registers are offered to each MAC unit, providing each with four possible
combinations of 16-bit input operands. Dual MAC operations are fre-
quently referred to as vector operations, because a program could store
vectors of samples in the four input operands and perform vector
computations.
An example of a dual multiply and accumulate instruction is
A1 += R1.H * R2.L, A0 += R1.L * R2.H ;
This instruction represents two multiply and accumulate operations.
• In one operation (MAC1) the high half of
low half of
• In the second operation (MAC0) the low half of
the high half of
The results of the MAC operations may be written to registers in a num-
ber of ways: as a pair of 16-bit halves, as a pair of 32-bit registers, or as an
independent 16-bit half register or 32-bit register.
For example:
R3.H = (A1 += R1.H * R2.L), R3.L = (A0 += R1.L * R2.L) ;
In this instruction, the 40-bit Accumulator is packed into a 16-bit half
register. The result from MAC1 must be transferred to a high half of a
destination register and the result from MAC0 must be transferred to the
low half of the same destination register.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and added to the contents of the
R2
and added to the contents of
R2
Computational Units
is multiplied by the
R1
Accumulator.
A1
is multiplied by
R1
.
A0
2-47
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